library IEEE;
-- Hier komen de gebruikte libraries:
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity pwm_generator is
	port (	clk		: in	std_logic;
		reset		: in	std_logic;
		direction	: in	std_logic;
		count_in	: in	std_logic_vector (19 downto 0);
		
		

		pwm		: out	std_logic
	);
end entity pwm_generator;


architecture behavioural of pwm_generator is
   type pwm_state is (OFF_STATE, ON_STATE);
   signal state, newstate: pwm_state;
   
   constant REVERSE_COUNT : std_logic_vector(19 downto 0) := std_logic_vector(to_unsigned(5e4,20)); --5e4
   constant FRONT_COUNT : std_logic_vector(19 downto 0) := std_logic_vector(to_unsigned(1e5,20));--1e5
   constant ZERO_COUNT : std_logic_vector(19 downto 0) := std_logic_vector(to_unsigned(0, 20));
begin
  lbl1: process(clk)
  begin
       if (rising_edge (clk)) then
           if (reset = '1') then 
             state <= OFF_STATE;
           else
             state <= newstate;
           end if;
       end if;
  end process;
  
  lblstate: process(state, reset, direction, count_in)
  begin
  case state is 
    when ON_STATE =>
      pwm <= '1';
      if (direction = '0' AND count_in = REVERSE_COUNT) then
        newstate <= OFF_STATE;
      elsif (count_in = FRONT_COUNT) then 
        newstate <= OFF_STATE;
      else 
        newstate <= ON_STATE;
      end if;
    when OFF_STATE =>
      pwm <= '0';
      if (count_in = ZERO_COUNT) then
        newstate <= ON_STATE;
      else 
        newstate <= OFF_STATE;
      end if;
        
    end case;
  end process;
  

    
end architecture behavioural;
